1. Field of the Invention
This application is related to delay lines and delay-locked loops.
2. Description of the Related Art
High speed memory interfaces employ delay lines to position data with respect to clock and/or clocks with respect to data to meet system timing requirements. A delay line typically includes a series of delay cells, where the delay through each cell can be varied. Delay lines can be configured in a delay-locked loop (DLL), which automatically adjusts the voltage/current in the delay cell, so that the total delay of the delay line tracks the frequency of a reference signal supplied to the DLL. When the delay line supplies an output signal having the desired frequency and phase, the DLL is said to be locked.
High accuracy may be required for clock signals in high speed memory interfaces. One design challenge for memory interfaces is that the DLL input signal data rate is aperiodic. However, the DLL delay needs to accurately maintain its delay independent of data rate. That is, the delay of a delay line utilized in a memory interface needs to remain constant even in the absence of an input signal. In some prior art solutions, in order to accomplish this, a DLL is provided for one or more other delay lines. Thus, one delay line is driven continuously by a reference clock and is part of a closed loop feedback system (i.e., it is configured as a DLL). The other delay line is a replica of the first and is operated open loop with the receive data acting as the input signal. The control voltage/current that determines the delay of the delay cells for the DLL is also applied to the delay cells of the associated replica delay line. However, that has the disadvantage of having multiple delay lines, which utilizes additional power and space on an integrated circuit.